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92504tn (ot) no.8013-1/11 ! any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft?s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. ! sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. sanyo electric co., ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan sanyo semiconductors data sheet LC723341E cmos ic ? ? ? ? etr controller overview the LC723341E is a single-chip microcontroller/electronic tuner that also integrates a 250 mhz pll circuit and a 1/4-duty 1/2-bias lcd driver on the same chip. functions ? program memory (rom): 4096 16 bits (8 kb) ? data memory (ram): 256 4 bits ? cycle time: 1.33 s (all one-word instructions) at 4.5 mhz ? stack: 8 levels ? lcd driver: 48 to 80 segments (1/4-duty 1/2-bias drive) ? interrupts: external interrupts: 2 systems timer interrupts: 2 systems (1, 5, 10 or 50 ms) ? a/d converter: four input channels (6-bit successive approximation conversion) ? dedicated input ports: 8 ports (of which 4 can be switched for use as a/d converter inputs) ? dedicated output ports: 10 ports (of which 6 are open-drain ports and 4 can be switched between cmos and open- drain specifications) ? i/o ports: 19 ports (of which 8 can be switched for use as segment ports) ? pll: reference frequencies: 3, 3.125, 5, 6.25, 12.5 and 25 khz supports dead zone control (4 types) and features a built-in unlock detection circuit. ? input frequency (input sensitivity): fm band - 10 to 250 mhz am band- 0.5 to 40 mhz ? input sensitivity: fm band - 35 mv rms (above 130 mhz: 50 mv rms) am band - 35 mv rms ? if counting: hctr input - 0.4 to 12 mhz (35 mv rms) ? external reset input: the program counter starts from location 0 during cpu and pll operation ? reset: built-in voltage detection reset circuit ? halt mode: the controller's operating clock is temporarily slowed to reduce current drain. ? backup mode: the crystal oscillator is stopped. ? static power on function: backup mode is cleared using the pf port. ? beep tone: frequencies of 0.75, 1.25, 1.5, 2.08. 2.5, 3.125, and 6.25 khz ? memory retention voltage: 0.9 v or higher ? vdd: pll 4.5 to 5.5 v cpu 3.5 to 5.5 v ? package: qip64e (0.8 mm pitch) ordering number : enn8013
LC723341E no.8013-2/11 specifications absolute maximum ratings at ta = 25 c, v ss = 0 v parameter symbol conditions ratings unit maximum supply voltage v dd max ? 0.3 to +6.5 v input voltage v in all input pins ? 0.3 to vdd to +0.3 v v out 1 pe2, pl0 to pl3 ? 0.3 to +15 v output voltage v out 2 all output pins except v out 1 ? 0.3 to vdd + 0.3 v i out 1 pc, pd, pe3, pg, ph, pk, eo 0 to 3 ma i out 2 pb 0 to 1 ma i out 3 pe2, pl0 to pl3 0 to 2 ma i out 4 s1 to s20 0 to 1 a output current i out 5 com1 to com4 3 ma allowable power dissipation pdmax ta = ? 20 to +70 c 300 mw operating temperature topr ? 20 to +70 c storage temperature tstg ? 45 to +125 c package dimensions unit: mm 3159a 14.0 17.2 14.0 17.2 0.15 0.35 0.8 (2.7) 3.0max 0.1 0.8 (1.0) 116 17 32 33 48 49 64 sanyo : qip64e (14 14)
LC723341E no.8013-3/11 allowable operating ranges at ta = -20 to +70 c, v dd = 2.6 to 5.5v ratings parameter symbol conditions min typ max unit v dd 1 pll operating voltage 4.5 5.5 v dd 2 memory retention voltage 0.9 5.5 supply voltage v dd 3 cpu operating voltage 2.6 5.5 v v ih 1 input ports other than v ih 2, v ih 3, amin, fmin, hctr, and xin 0.7v dd v dd v v ih 2bres 0.8v dd v dd v high-level input voltage v ih 3 the pf port 0.6v dd v dd v v il 1 input ports other than v il 2, v il 3, amin, fmin, hctr, and xin 00.3v dd v v il 2 bres 0 0.2v dd v low-level input voltage v il 3 the pf port 0 0.2v dd v v in 1 xin 0.5 1.5 vrms v in 2fmin: f in 2, amin 0.035 0.35 vrms v in 3fmin: f in 3 0.05 0.35 vrms input amplitude v in 4 hctr 0.035 0.35 vrms input voltage range v in 5 adi0, adi1, adi2, adi3 0 v dd v f in 1 xin 4.0 4.5 5.0 mhz f in 2fmin: v in 2, v dd 1 10 130 mhz f in 3fmin: v in 3, v dd 1 130 250 mhz f in 4 amin(h): v in 2, v dd 1240mhz f in 5amin(l): v in 2, v dd 10.510mhz input frequency f in 6 hctr: v in 4, v dd 10.415mhz
LC723341E no.8013-4/11 electrical characteristics under the allowable operating conditions ratings parameter symbol conditions min typ max unit i ih 1xin: v i = v dd = 5.0v 2.0 5.0 15 a i ih 2 fmin, amin, hctr: v i = v dd = 5.0v 4.0 10 30 a high-level input current i ih 3 ports pa (pull-down resistors disabled), pc, pd, pf, pg, ph, and pk. bres: v i = v dd = 5.0 v. 3 a i il 1xin: v i = v dd = v ss ? 2.0 ? 5.0 ? 15 a i il 2 fmin, amin, hctr: v i = v dd = v ss ? 4.0 ? 10 ? 30 a low-level input current i il 3 ports pa (pull-down resistors disabled), pc, pd, pf, pg, ph, and pk. bres: v i = v dd = v ss . ? 3 a input floating voltage v if pa. pull-down resistors enabled 0.05v dd v r pd 1 pa pull-down resistors. v dd = 5.0 v 75 100 200 k ? pull-down resistance r pd 2 test1 resistance 10 k ? hysteresis v h bres 0.1v dd v v oh 1 pb: io = 1ma v dd ? 2.0 v dd ? 1.0 v v oh 2 pc, pd, pe3, pg, ph, pk: i o = 1ma v dd ? 1.0 v v oh 3 eo: i o = 500 av dd ? 1.0 v v oh 4xout: i o = 200 av dd ? 1.0 v v oh 5 s1 to s20: i o = 100 av dd ? 1.0 v high-level output voltage v oh 6 com1, com2, com3, com4: i o = 5 av dd ? 0.75 v dd ? 0.5 v v ol 1 pb: i o = ? 50 a 1.0 2.0 v v ol 2 pc, pd, pe3, pg, ph, pk: i o = ? 1ma 1.0 v v ol 3 eo: i o = ? 500 a 1.0 v v ol 4xout: i o = ? 200 a 1.0 v v ol 5 s1 to s20: i o = ? 100 a 1.0 v v ol 6 com1, com2, com3, com4: i o = ? 5 a 0.5 0.75 v low-level output voltage v ol 7 pe2, pl0 to pl3: io = 5ma 2.0 v i off 1 the pb, pc, pd, pe3, pg, ph, pk, and eo ports ? 3+3 a output off leakage current i off 2 pe2, pl0 to pl3 ? 100 +100 na output mid-level voltage v m com1, com2, com3, com4: v dd = 5.0v 2.0 2.5 3.0 v a/d conversion error adi0, adi1, adi2, adi3 ? 1/2 +1/2 lsb power down detection voltage v det 2.7 3.0 3.3 v i dd 1v dd 1: f in 2 130mhz ta = 25c 15 20 ma i dd 2v dd 3: halt mode, ta = 25c *1 0.6 ma i dd 3v dd = 5.5 v, oscillator stopped, ta = 25c *2 5 a current drain i dd 4v dd = 2.5 v, oscillator stopped, ta = 25c *2 1 a note: the halt mode current is used to execute 20 instruction steps every 125 ms.
LC723341E no.8013-5/11 *1 halt and pll stop mode current measurement conditions *2 backup mode current measurement conditions a a 30 pf fmin xin amin hctr test1 xout vdd bres vss pa, pf with all ports other than those mentioned above left open. with output mode selected for pc and pd. with segment mode selected for s13 to s20. set up halt mode with a software instruction. the state where cpu operation is stopped without stopping the crystal oscillator. 30 pf 4.5mhz 30 pf bres fmin xin amin hctr test1 xout vdd vss with all ports other than those mentioned above left open. with output mode selected for pc and pd. with segment mode selected for s13 to s20. set up backup mode with a software instruction. the state where the crystal oscillator is stopped. 4.5mhz 30 pf
LC723341E no.8013-6/11 pin assignment 54 55 60 61 62 63 64 1 2 3 49 50 51 52 53 58 59 56 57 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 22 21 20 19 25 24 23 28 27 26 34 33 32 31 30 29 36 35 38 37 42 41 40 39 45 44 43 48 47 46 xou t test1 pa3 pa2 pa1 pa0 pb3 pb2 pb1 pb0 pc3 pc2 pc1 pc0 pd3 pd2 s17/pg0 s18/pg1 s19/pg2 s20/pg3 pk0 pk1 pk2 vss adi0/pf0 adi1/pf1 adi2/pf2 adi3/pf3 pe2 beep/pe3 int0 /pd0 int1 /pd1 pl3 pl2 pl1 pl0 xin fmin a min vss com4 com3 com2 com1 bres hct r vdd eo s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 / ph0 s14 / ph1 s15 / ph2 s16 / ph3 general-purpose i/o pins general-purpose unbalanced outputs open-drain outputs general-purpose inputs LC723341E general-purpos e input general-purpos e i/o pins open-drain pins open-drai n pins general-purpose i/o pins segment outputs top vie w
LC723341E no.8013-7/11 block diagram phase detector reference divider divider system clock generator programmble divider 1/16, 1/17 vdet bank address decoder data bus timer 0 judge alu cf skip bank latch stack 12 12 address counter address decoder rom 4k 16 bits bus control jmp cal return interrupt reset instruction decoder pll data latch pll control data latch / bus drive r data latch / bus drive r bus driver xin xout fmin pc2 pc1 pc0 pc3 pa3 pa2 pa1 pa0 test1 res * amin s16/ph3 s15/ph2 s13/ph0 s14/ph1 lcd port driver lcda/b eo s12 s1 vss pb2 pb1 pb0 pb3 * latch pe3/beep com1 com2 com3 com4 s20/pg3 s19/pg2 s17/pg0 s18/pg1 data latch / bus drive r mpx (6 bits) mpx mpx beep tone common driver data latch / bus driver data latch / bus drive r data latch / bus drive r 80 pf2/adi2 pf1/adi1 pf0/adi0 data latch / bus drive r pd2 int 1 /pd1 int0 /pd0 pd3 pe2 pf3/adi3 data latch / bus drive r p k 1 p k 0 p k 2 * 1/2 hctr universal counter (20 bits) vdd timer 1 latch data latch / bus drive r pl0 pl1 pl2 pl3 1/2 ram 256 4 bits
LC723341E no.8013-8/11 pin functions pin no. symbol i/o description equivalent circuit 64 1 xin xout i o 4.5 mhz crystal oscillator circuit connections 2 test1 i ic test pin this pin must be connected to ground during normal operation. ? 6 5 4 3 pa0 pa1 pa2 pa3 i these input ports are used as the key return ports and are designed with a low threshold voltage. when a key matrix is formed with the pb port, multiple key presses with up to 3 keys can be detected. the four pull-down resistors are enabled/disabled together with an ios instruction (pwn = 2, b1). the pull-down resistors cannot be controlled individually. in backup mode, this port goes to the input disabled state, and the pull-down resistors will be in the disabled state after a reset. input with built-in pull-down resistor 10 9 8 7 pb0 pb1 pb2 pb3 o these output ports are used as the key source ports and can be set up to be either unbalanced outputs or open-drain outputs. the output type is set with an ios instruction (pwn = 2, b0, b2, b3). when used set to the unbalanced output circuit type, diodes to prevent short circuits due to multiple key presses are not required. if used set to the open- drain output circuit type, pull-up resistors between vdd and the port pins are required. in backup mode, this port goes to the output high-impedance state. after a reset, this port will be in the output high-impedance state, and will remain in that state until an output instruction (an out, spb, or rpb instruction) is executed. *: note that the output impedance requires care if these pins are used for any purpose other than as key source outputs. unbalanced cmos push-pull or n-channel open-drain output 15 14 13 12 pc0 pc1 pc2 pc3 i/o general-purpose i/o ports. *1 the ios instruction (pwn = 4) is used to switch between the general-purpose input and output port functions. the i/o direction can be set in 1-bit units. (0: input, 1: output) in backup mode, this port goes to the input disabled high-impedance state. after a reset, the general-purpose input port function will be selected. cmos push-pull circuit 18 17 16 15 pd0/ int0 pd1/ int1 pd2 pd3 i/o general-purpose i/o ports. *1 the ios instruction (pwn = 5, b0, b1) is used to switch between the general-purpose input and output port functions. the i/o direction can be set in 1-bit units. (0: input, 1: output) two of these port pins can be used as external interrupt inputs. in that case, the i/o direction must be set to input, and rising or falling edge detection must be selected with an ios instruction (pwn = 3, b0, b1). in backup mode, this port goes to the input disabled high-impedance state. after a reset, the general-purpose input port function will be selected. cmos push-pull circuit note: ? 1 when ports that can be switched between input and output are used as output ports, the output data must be established in adva nce with an out, spb, or rpb instruction before the port is set to output mode with an ios instruction. continued on next page.
LC723341E no.8013-9/11 continued from preceding page. pin no. symbol i/o description equivalent circuit 20 pe2 o pe2 is an open-drain output port. a pull-up resistor between this port and vdd is required. in backup mode, pe2 goes to the high-impedance state. after a reset, it remains at the low level until an output instruction is executed. n-channel open-drain output 18 pe3/beep o general-purpose output or beep tone output shared-function port. the beep instruction is used to switch between the general-purpose output and beep tone output functions. to use this port as a general-purpose output port, execute a beep instruction with b3 = 0 to set up the general-purpose output function. if b3 = 1, the beep tone output function will be selected. bits b0, b1, and b2 select the beep tone frequency. the LC723341E provides seven beep tone frequencies. *: when the pe3 port is set to the beep tone function, executing an output instruction only switches the state of the internal output latch and has no effect on the beep tone output. in backup mode, this port goes to the high-impedance state. this state is maintained until either an output instruction or a beep instruction is executed. after a reset, the general-purpose output port function will be selected. cmos push-pull output 24 23 22 21 pf0/adi0 pf1/adi1 pf2/adi2 pf3/adi3 i general-purpose input or a/d converter input shared-function ports. the ios instruction (pwn = fh, b0 to b3) is used to switch between the general-purpose input and a/d converter input functions. the function can be switched in 1-bit units. (0: general-purpose input, 1: a/d converter input) when the a/d converter input function is selected, the pin to be a/d converted is selected with the ios instruction (pwn = 1). the a/d converter is started with the ucc instruction (b3 = 1, b2 = 1). the adce flag is set when the conversion completes. the inr instruction is used to read out the data. *: since cmos input is disabled, the data read out will always be zero if an input instruction is executed for a port pin set to analog input mode. execute an ios instruction (pwn = 0, b0 to b3) to set the port that clears backup mode. in backup mode, this port goes to input disabled high-impedance state. after a reset, the general-purpose input port function will be selected. the conversion time for the 6-bit successive approximation a/d converter is 0.64 ms. the a/d converter full-scale voltage is 63/96 of vdd. cmos input or analog input 28 27 26 pk0 pk1 pk2 i/o these are general-purpose i/o ports. *1 the ios instruction (pwn = a) is used to switch between the general-purpose input and output port functions. the i/o direction can be set in 1-bit units. (0: input, 1: output) in backup mode, this port goes to the input disabled high-impedance state. after a reset, the general-purpose input port function will be selected. cmos push-pull circuit 32 31 30 29 36 35 34 33 s17/pg0 s18/pg1 s19/pg2 s20/pg3 s13/ph0 s14/ph1 s15/ph2 s16/ph3 i/o lcd driver segment output or general-purpose i/o shared-function ports. *1 the ios instruction is used to switch between the segment output and general-purpose i/o functions and for i/o direction switching for the general-purpose port function. ? when used as segment output ports pg port ... ios instruction (pwn = b, b0 to b3) 0: segment output ph port ... ios instruction (pwn = c, b0 to b3) 0: general-purpose i/o these pins can be switched in 1-bit units. ? when used as general-purpose i/o ports pg port ... ios instruction (pwn = 6, b0 to b3) 0: input ph port ... ios instruction (pwn = 7, b0 to b3) 1: output the i/o directions of these pins can be set in 1-bit units. in backup mode, when used as general-purpose output ports, the pins go to the input disabled high-impedance state. when used as segment outputs, these pins will be held fixed at the low level. after a reset, the segment output function will be selected. cmos push-pull circuit note: ? 1 when ports that can be switched between input and output are used as output ports, the output data must be established in adva nce with an out, spb, or rpb instruction before the port is set to output mode with an ios instruction. continued on next page.
LC723341E no.8013-10/11 continued from preceding page. pin no. symbol i/o description equivalent circuit 48-37 s1-s12 o lcd driver segment output pins. this driver implements 1/4-duty 1/2-bias drive. the frame frequency is 75 hz. in backup mode, after a reset, and after an lcd off instruction has been executed, these pins will be held fixed at the low level. cmos push-pull circuit 62 61 60 59 com1 com2 com3 com4 o lcd driver common output pins. this driver implements 1/4-duty 1/2-bias drive. the frame frequency is 75 hz. in backup mode, after a reset, and after an lcd off instruction has been executed, these pins will be held fixed at the low level. 69 bres system reset pin. if this pin is held low for at least one machine cycle during cpu operation or in halt mode, the system will be reset and execution will continue with the program counter set to location 0. 54 hctr i dedicated universal counter input port. ? for frequency measurement, select frequency measurement mode with the ucd instruction (b3 = 0, b2 = 0) and start the counter with the ucc instruction. the cntend flag will be set when the count completes. in this mode, the input operates as an ac amplifier. thus the input must be capacitance coupled. input is disabled in backup mode, in halt mode, during a reset, and in pll stop mode. cmos amplifier input 56 fmin i fm vco (local oscillator) input. this pin is selected using the pll instruction cw1 field. the input must be capacitor coupled. input is disabled in backup mode, in halt mode, during a reset, and in pll stop mode. cmos amplifier input 57 amin i am vco (local oscillator) input. this pin is selected and the bandwidth set using the pll instruction cw1 field. the input must be capacitor coupled. input is disabled in backup mode, in halt mode, during a reset, and in pll stop mode. cmos amplifier input 59 eo o this is the main charge pump output. when the frequency of the local oscillator divided by n is higher than the reference frequency, a high level is output, and when it is lower, a low level is output. this pin goes to the high-impedance state when the frequencies match. this pin goes to the output high-impedance state in backup mode, in halt mode, during a reset, and in pll stop mode. cmos push-pull circuit continued on next page. measurement time 1 1 1 0 0 1 32 ms 8 ms 4 ms 1 ms 0 0 ucs b1, b0 measurement time 1 0 0 1 hctr 0 0 measurement mode frequency ?? ucs b3, b2 ?? 0 0 band 10 to 250 mhz cw1 b1, b0 1 0 band 0.5 to 10 mhz (mw,lw) cw1 b1, b0 1 1 2 to 40 mhz (sw)
LC723341E no.8013-11/11 continued from preceding page. pin no. symbol i/o description equivalent circuit 63 62 61 60 pl0 pl1 pl2 pl3 o open-drain output port. pull-up resistors must be inserted between these port pins and vdd. these pins go to the high-impedance state in backup mode. after a reset, the output remains at the low level until an output instruction is executed. n-channel open-drain output 25 58 55 vss vss vdd ? power supply connections. connect the vss pins to the minus side (ground) of the power supply. connect the vdd pin to the plus side. ? ! specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. ! sanyo electric co., ltd. strives to supply high-quality high-reliab ility products. however, any and all semiconductor products fail with some probab ility. it is possible that these pr obab ilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. ! in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. ! no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, of otherwise, without the prior written permission of sanyo electric co., ltd. ! any and all information described or contained herein are subject to change without notice due to produc t/tec hnology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo product that you intend to use. ! information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of september, 2004. specifications and information herein are subject to change without notice.

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